I have spent some time trying to find out what options are being used for FPGA for p1. My goal is to extend the life of P1 on some projects where the needs are pretty simple: Get more pins with PortB, more cores, more memory per core or at least more hub.
Can the size of a core be increased above 2k. One of the reasons for this is to extend memory for LCD graphics that are constrained by core size.
What are people using for SMT (preferably non BGA) FPGA? 20-30 bucks max is not an issue. I prefer pins outside the chip for easier fixes if needed, but QFN is OK.
Logic elements needed for the bare minimum request of PortB + 16cores? I see MAX10 comes in a number or sizes.
Has anyone here actually built their own boards with an FPGA?
I use BSTC for optimizing large programs, and assume that the FPGA does not care where the binary comes from but I use Silabs CP2110 for programming the binary, so does the loading work exactly the same so that the hardware and software I use for USB loading can remain unchanged?
From what I read the only limitation is no ROM fonts. Should the r/c DACs behave identically using the FPGA pins?
Can the size of a core be increased above 2k. One of the reasons for this is to extend memory for LCD graphics that are constrained by core size.
What are people using for SMT (preferably non BGA) FPGA? 20-30 bucks max is not an issue. I prefer pins outside the chip for easier fixes if needed, but QFN is OK.
Logic elements needed for the bare minimum request of PortB + 16cores? I see MAX10 comes in a number or sizes.
Has anyone here actually built their own boards with an FPGA?
I use BSTC for optimizing large programs, and assume that the FPGA does not care where the binary comes from but I use Silabs CP2110 for programming the binary, so does the loading work exactly the same so that the hardware and software I use for USB loading can remain unchanged?
From what I read the only limitation is no ROM fonts. Should the r/c DACs behave identically using the FPGA pins?